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LTC3541 1 3541f high ef ciency buck + vldo regulator pdas/palmtop pcs digital cameras cellular phones pc cards wireless and dsl modems other portable power systems high ef? ciency, 500ma buck plus 300ma vldo tm regulator auto start-up powers buck output prior to vldo/linear regulator output independent high ef? ciency, 500ma buck (v in : 2.7v to 5.5v) 300ma vldo regulator with 30ma standalone mode no external schottky diodes required buck output voltage range: 0.8v to 5v vldo input voltage range (lv in ): 0.9v to 5.5v vldo output voltage range vldo: 0.4v to 4.1v selectable fixed frequency, pulse-skip operation or burst mode ? operation short-circuit protected current mode operation for excellent line and load transient response constant frequency operation: 2.25mhz low dropout buck operation: 100% duty cycle small, thermally enhanced, 10-lead (3mm 3mm) dfn package applicatio s u features descriptio u typical applicatio u , lt, ltc and ltm are registered trademarks of linear technology corporation. vldo is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6611131, 6304066, 6498466, 6580258 the ltc ? 3541 combines a synchronous buck dc/dc converter with a very low dropout linear regulator (vldo) to provide up to two output voltages from a single input voltage with minimal external components. when con? gured for dual output operation, the LTC3541s auto start-up feature will bring the buck output into regulation in a controlled manner prior to enabling the vldo regulator output without the need for external pin control. vldo/ linear regulator output prior to buck output sequencing may also be obtained via external pin control. the input voltage range is ideally suited for li-ion battery-powered applications, as well as powering sub-3.3v logic from 5v or 3.3v rails. the synchronous buck converter provides a high ef? ciency output, typically 90%, capable of providing up to 500ma of continuous output current while switching at 2.25mhz, allowing the use of small surface mount inductors and ca- pacitors. a mode-select pin allows burst mode operation to be enabled for higher ef? ciency at light load currents, or disabled for lower noise, constant frequency operation. the vldo regulator provides a low noise, low voltage output capable of providing up to 300ma of continuous output current using only a 2.2f ceramic capacitor. the input supply voltage of the vldo regulator (lv in ) may come from the buck regulator or a separate supply. sw v in enbuck buckfb lv in envldo mode gnd lfb lv out pgnd LTC3541 150k v out2 1.5v 300ma 2.2 f 115k 3541 ta01a 2.2 h 10 f v in 2.9v to 5.5v 243k 22pf 412k v out1 2.5v 500ma LTC3541 typical application buck (burst) ef? ciency and power loss vs load current load current (ma) 1 40 efficiency (%) power loss (w) 50 60 70 80 10 100 1000 3541 ta01b 30 20 10 0 90 100 0.001 0.01 0.1 0.0001 1 v in = 3.3v v out = 2.5v efficiency power loss
LTC3541 2 3541f supply voltages: v in , lv in .................................................. C0.3v to 6v lv in C v in ..........................................................<0.3v pin voltages: envldo, enbuck, mode, sw, lfb, buckfb .............................C0.3v to (v in + 0.3v) linear regulator i out(max) (100ms) (note 9) ......100ma operating ambient temperature range (note 2) .................................................... C40c to 85c junction temperature (note 5) ............................. 125c storage temperature range ................... C65c to 125c (note 1) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.6v unless otherwise speci? ed (note 2) electrical characteristics absolute axi u rati gs w ww u package/order i for atio uu w top view 11 dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 sw envldo mode gnd lv in v in enbuck buckfb lfb lv out t jmax = 125c, ja = 43c/w exposed pad (pin 11) is gnd, must be soldered to pcb order part number dd part marking LTC3541edd lcbs order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts speci? ed with wider operating temperature ranges. symbol parameter conditions min typ max units i pk peak inductor current v in = 4.2v (note 8) 0.8 0.95 1.25 a i buckfb buckfb pin input current v buckfb = 0.9v 50 na i lfb lfb pin input current v lfb = 0.45v C200 C40 na v in input voltage range (note 4) 2.7 5.5 v v in(linereg) buck v in line regulation v in = 2.7v to 5.5v, enbuck = v in , envldo = 0v, mode = v in (note 6) 0.04 0.4 %/v vldo v in line regulation (referred to lfb) v in = 2.7v to 5.5v, lv out = 1.2v, enbuck = v in , envldo = v in , i out(vldo) = 100ma, lv in = 1.5v 0.6 mv/v linear regulator v in line regulation (referred to lfb) v in = 2.7v to 5.5v, lv out = 1.2v, enbuck = 0v, envldo = v in , i out(lreg) = 10ma 0.6 mv/v lv in(linereg) lv in line regulation (referred to lfb) lv in = 0.9v to 5.5v, v in = 5.5v, lv out = 0.4v, enbuck = v in , envldo = v in , mode = v in , i out(vldo) = 100ma 0.3 mv/v vldo do lv in C lv out dropout voltage (note 9) lv in = 1.5v, enbuck = v in , envldo = v in , mode = v in , i out(vldo) = 50ma, v lfb = 0.3v 28 60 mv v loadreg buck output load regulation enbuck = v in , envldo = 0v, mode = v in (note 6) 0.5 % vldo output load regulation i out(vldo) = 1ma C 300ma, lv in = 1.5v, lv out = 1.2v, enbuck = v in , envldo = v in , mode = v in 0.25 0.5 % linear regulator output load i out(lreg) = 1ma C 30ma, lv out = 1.2v, enbuck = 0v, envldo = v in 0.25 0.5 % v buckfb reference regulation voltage (note 6) enbuck = v in , envldo = 0v, t a = 25c 0.784 0.8 0.816 v enbuck = v in , envldo = 0v, 0c t a 85c 0.782 0.8 0.818 v enbuck = v in , envldo = 0v, C40c t a 85c 0.78 0.8 0.82 v v lfb reference regulation voltage (note 7) enbuck = 0v, envldo = v in , t a = 25c 0.392 0.4 0.408 v enbuck = 0v, envldo = v in , 0c t a 85c 0.391 0.4 0.409 v enbuck = 0v, envldo = v in , C40c t a 85c 0.390 0.4 0.410 v
LTC3541 3 3541f the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.6v unless otherwise speci? ed (note 2) electrical characteristics symbol parameter conditions min typ max units i s buck + vldo burst mode sleep v in quiescent current lv in = 1.5v, lv out = 1.2v, enbuck = v in , envldo = v in , mode = 0v, i out(vldo) = 10a, v buckfb = 0.9v 85 a buck + vldo burst mode active v in quiescent current lv in = 1.5v, lv out = 1.2v, enbuck = v in , envldo = v in , mode = 0v, i out(vldo) = 10a, v buckfb = 0.7v 315 a buck + vldo pulse-skip mode active v in quiescent current lv in = 1.5v, lv out = 1.2v, enbuck = v in , envldo = v in , mode = v in , i out(vldo) = 10a, v buckfb = 0.7v 300 a buck burst mode sleep v in quiescent current v buckfb = 0.9v, i out(buck) = 0a, enbuck = v in , envldo = 0v, mode = 0v 55 a buck burst mode active v in quiscent current v buckfb = 0.7v, i out(buck) = 0a, enbuck = v in , envldo = 0v, mode = 0v 300 a buck pulse-skip mode active v in quiescent current v buckfb = 0.7v, i out(buck) = 0a, enbuck = v in , envldo = 0v, mode = v in 285 a linear regulator v in quiescent current lv out = 1.2v, enbuck = 0v, envldo = v in , i out(lreg) = 10a 50 a v in shutdown quiescent current enbuck = 0v, envldo = 0v 2.5 a lv in shutdown quiescent current lv in = 3.6v, enbuck = 0v, envldo = 0v 0.1 a f osc oscillator frequency 1.8 2.25 2.7 mhz r pfet r ds(on) of p-channel mosfet i sw = 100ma 0.25 r nfet r ds(on) of n-channel mosfet i sw = 100ma 0.35 i lsw sw leakage enable = 0v, v sw = 0v or 6v, v in = 6v 0.01 1 a v ih input pin high threshold mode, enbuck, envldo 0.9 v v il input pin low threshold mode, enbuck, envldo 0.3 v i mode , i enbuck , i envldo input pin current 0.01 1 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3541 is guaranteed to meet performance speci? cations from 0c to 85c. vldo/linear regulator output is tested and speci? ed under pulse load conditions such that t j t a , and are 100% production tested at 25c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: minimum operating lv in voltage required for vldo regulator regulation is: lv in lv out + v dropout and lv in 0.9v note 4: minimum operating v in voltage required for vldo regulator and linear regulator regulation is: v in lv out + 1.4v and v in 2.7v note 5: t j is calculated from the ambient temperature, t a , and power dissipation, p d , according to the following formula: t j = t a + (p d ? 43c/w) note 6: the LTC3541 is tested in a proprietary test mode that connects v buckfb to the output of the error ampli? er. for the reference regulation and line regulation tests, the output of the error ampli? er is set to the midpoint. for the load regulation test, the output of the error ampli? er is driven to minimum and maximum of the signal range. note 7: measurement made in closed loop linear regulator con? guration with lv out = 1.2v, i load = 10a. note 8: measurement made in a proprietary test mode with slope compensation disabled. note 9: measurement is assured by design, characterization and statistical process control. note 10: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability.
LTC3541 4 3541f ef? ciency vs input voltage for buck (burst) ef? ciency vs input voltage for buck (pulse skip) ef? ciency vs load current for buck (burst) ef? ciency vs load current for buck (pulse skip) ef? ciency vs load current for buck (burst) typical perfor a ce characteristics uw input voltage (v) 2 50 efficiency (%) 55 65 70 75 100 85 3 4 3541 g01 60 90 95 80 5 6 v out = 1.8v i out = 500ma i out = 30ma i out = 100ma input voltage (v) 2 50 efficiency (%) 55 65 70 75 100 85 3 4 3541 g02 60 90 95 80 5 6 v out = 1.8v i out = 500ma i out = 30ma i out = 100ma load current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3541 g03 0 1 v out = 1.8v v in = 2.7v v in = 4.2v v in = 3.6v load current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3541 g04 0 1 v out = 1.8v v in = 2.7v v in = 4.2v v in = 3.6v load current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3541 g05 0 1 v out = 2.5v v in = 2.7v v in = 4.2v v in = 3.6v ef? ciency vs load current for buck (pulse skip) load current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3541 g06 0 1 v out = 2.5v v in = 2.7v v in = 4.2v v in = 3.6v vldo dropout voltage vs load current buck (burst) plus vldo bias current vs vldo load current output (auto start-up sequence, buck in pulse skip) vs time load current (ma) 0 0 dropout voltage (mv) 20 40 60 80 100 50 100 150 200 3541 g07 250 300 v in = 4.2v v in = 3v v out = 1.5v v in = 3.6v load current (ma) 0.1 bias current ( a) 100 150 1000 3541 g08 50 0 1 10 100 250 200 v in = 3.6v i load(buck) = 0 i bias = i vin + i lvin C i load v out 2v/div lv out 2v/div v in 2v/div i vout = 300ma i lvout = 200ma 2ms/div 3541 g09
LTC3541 5 3541f typical perfor a ce characteristics uw oscillator frequency vs temperature oscillator frequency vs supply voltage buck reference vs temperature r ds(on) vs temperature buck (pulse skip) load step from 1ma to 500ma buck (burst) and vldo output temperature ( c) C50 2.00 frequency (mhz) 2.05 2.15 2.20 2.25 2.50 2.35 0 50 75 3541 g10 2.10 2.40 2.45 2.30 C25 25 100 125 v in = 3.6v supply voltage (v) 3 frequency (mhz) 2.2 2.3 3541 g11 2.1 2.0 4 5 6 2.5 v in = 3.6v 2.4 temperature ( c) C50 0.390 reference (v) 0.392 0.396 0.398 0.400 0.410 0.404 0 50 75 5341 g12 0.394 0.406 0.408 0.402 C25 25 100 125 v in = 3.6v vldo/linear regulator reference vs temperature temperature ( c) C50 0.780 reference (v) 0.784 0.792 0.796 0.800 0.820 0.808 0 50 75 5341 g13 0.788 0.812 0.816 0.804 C25 25 100 125 v in = 3.6v temperature ( c) C50 0.400 0.500 0.700 25 75 3541 g14 0.300 0.200 C25 0 50 100 125 0.100 0 0.600 r ds(on) ( ? ) v in = 2.5v v in = 3.6v v in = 5.5v synch switch main switch v out 10mv/div ac coupled lv out 10mv/div ac coupled v in = 3.6v lv out = 1.5v v out = 1.8v i load = 50ma burst mode operation 2 s/div 3541 g15 v out 100mv/div ac coupled i l 500ma/div i load 500ma/div v in = 3.6v v out = 1.8v i load = 1ma to 500ma 40 s/div 3541 g16 v out 100mv/div ac coupled i l 500ma/div i load 500ma/div v in = 3.6v v out = 1.8v i load = 1ma to 500ma 40 s/div 3541 g17 lv out 20mv/div ac coupled i load 250ma/div v in = 3.6v lv out = 1.5v i load = 1ma to 300ma 400 s/div 3541 g18 buck (burst) load step from 1ma to 500ma vldo load step from 1ma to 500ma
LTC3541 6 3541f typical perfor a ce characteristics uw vldo load step from 100ma to 300ma linear regulator to vldo transient step, load = 1ma linear regulator to vldo transient step, load = 30ma lv out 20mv/div ac coupled i load 250ma/div v in = 3.6v lv out = 1.5v i load = 100ma to 300ma 400 s/div 3541 g19 lv out 10mv/div ac coupled i load 50ma/div v in = 3.6v lv out = 1.5v i load = 1ma 40 s/div 3541 g20 lv out 10mv/div ac coupled i load 50ma/div v in = 3.6v lv out = 1.5v i load = 30ma 40 s/div 3541 g21 vldo to linear regulator transient step, load = 1ma vldo to linear regulator transient step, load = 30ma lv out 10mv/div ac coupled i load 50ma/div v in = 3.6v lv out = 1.5v i load = 1ma 40 s/div 3541 g22 lv out 10mv/div ac coupled i load 50ma/div v in = 3.6v lv out = 1.5v i load = 30ma 40 s/div 3541 g23
LTC3541 7 3541f pi fu ctio s uuu table 1. LTC3541 control pin truth table pin name operational description enbuck envldo mode 0 0 x LTC3541 powered down 0 1 x buck powered down, vldo regulator powered down, linear regulator enabled 1 0 0 buck enabled, vldo regulator powered down, linear regulator powered down, burst mode operation 1 0 1 buck enabled, vldo regulator powered down, linear regulator powered down, pulse-skip mode operation 1 1 0 buck enabled, vldo regulator enabled, linear regulator powered down, burst mode operation 1 1 1 buck enabled, vldo regulator enabled, linear regulator powered down, pulse- skip mode operation v in (pin 1): main supply pin. this pin must be closely decoupled to gnd with a 10f or greater capacitor. enbuck (pin 2): buck enable pin. this pin enables the buck regulator when driven to a logic high. buckfb (pin 3): buck regulator feedback pin. this pin receives the buck regulators feedback voltage from an external resistive divider. lfb (pin 4): vldo/linear regulator feedback pin. this pin receives either the vldo or linear regulators feedback voltage from an external resistive divider. lv out (pin 5): vldo/linear regulator output pin. this pin provides the regulated output voltage from the vldo or linear regulator. lv in (pin 6): vldo/linear regulator input supply pin. this pin provides the input supply voltage for the vldo power fet. gnd (pin 7): analog ground pin. mode (pin 8): buck mode selection pin. this pin enables buck pulse-skip operation when driven to a logic high or left ? oating and enables buck burst mode operation when driven to a logic low. envldo (pin 9): vldo/linear regulator enable pin. when driven to a logic high, this pin enables the linear regulator when the enbuck pin is driven to a logic low, and enables the vldo when the enbuck pin is driven to a logic high. sw (pin 10): switch node pin. this pin connects the internal main and synchronous power mosfet switches to the external inductor for the buck regulator. exposed pad (pin 11): ground pin. this pin must be soldered to the pcb to provide both electrical contact to ground and good thermal contact to the pcb. note: table 1 details the truth table for the control pins of the LTC3541.
LTC3541 8 3541f operatio u the LTC3541 contains a high ef? ciency synchronous buck converter, a very low dropout regulator (vldo) and a linear regulator. it can be used to provide up to two output voltages from a single input voltage making the LTC3541 ideal for applications with limited board space. the combination and con? guration of these major blocks within the LTC3541 is determined by way of the control pins enbuck and envldo as de? ned in table 1. with the enbuck pin driven to a logic high and envldo driven to a logic low, the LTC3541 enables the buck con- verter to ef? ciently reduce the voltage provided at the v in input pin to an output voltage which is set by an external feedback resistor network. the buck regulator can be con- ? gured for pulse-skip or burst mode operation by driving the mode pin to a logic high or logic low respectively. the buck regulator is capable of providing a maximum output current of 500ma, which must be taken into consideration when using the buck regulator to provide the power for both the vldo and for external loads. with the enbuck pin driven to a logic low and envldo driven to a logic high, the LTC3541 enables the linear regulator, providing a low noise regulated output voltage at the lv out pin while drawing minimal quiescent current from the v in input pin. this feature allows output voltage lv out to be brought into regulation without the presence of the lv in voltage. with the enbuck and envldo pins both driven to a logic high, the LTC3541 enables the high ef? ciency buck converter and vldo regulator, providing dual output opera- tion from a single input voltage. when con? gured in this manner, the LTC3541s auto start-up sequencing feature will bring the buck output into regulation in a controlled manner prior to enabling the vldo regulator without the fu ctio al block diagra wu u C + vldo/linear reg lfb 3541 f01 pgnd gnd 500ma buck sw v in ref envldo mode fb gnd pgnd ref ref lfb cntrl gnd lv in v in control logic 4 lv in 6 buckfb i out(buck) = 500ma lv out 5 8 enbuck v in v in(min) lv out + 1.4v sw 1 10 10 f 22pf 2.2 f lv out(max) < v in C 1.4v i out = 300ma (vldo reg) i out = 30ma (linear reg) 2.2 h 11 7 3 2 9 figure 1. LTC3541 functional block diagram
LTC3541 9 3541f operatio u need for external pin control. a detailed discussion of the transitions between the vldo and linear regulator can be found in the vldo/linear regulator loop section. buck regulator control loop the LTC3541 internal buck regulator uses a constant fre- quency, current mode, step-down architecture. both the main (top, p-channel mosfet) and synchronous (bottom, n-channel mosfet) switches are internal. during normal operation, the internal main switch is turned on at the be- ginning of each clock cycle provided the internal feedback voltage to the buck is less than the reference voltage. the current into the inductor provided to the load increases until the current limit is reached. once the current limit is reached the main switch turns off and the energy stored in the inductor ? ows through the bottom synchronous switch into the load until the next clock cycle. the peak inductor current is determined by comparing the buck feedback signal to an internal 0.8v reference. when the load current increases, the output of the buck and hence the buck feedback signal decrease. this decrease causes the peak inductor current to increase until the aver- age inductor current matches the load current. while the main switch is off, the synchronous switch is turned on until either the inductor current starts to reverse direction or the beginning of a new clock cycle. when the mode pin is driven to a logic low, the LTC3541 buck regulator operates in burst mode operation for high ef? ciency. in this mode, the main switch operates based upon load demand. in burst mode operation the peak inductor current is set to a ? xed value, where each burst event can last from a few clock cycles at light loads to nearly continuous cycling at moderate loads. between burst events the main switch and any unneeded circuitry are turned off, reducing the quiescent current. in this sleep state, the load is being supplied solely from the output capacitor. as the output voltage droops, an internal error ampli? ers output rises until a wake threshold is reached causing the main switch to again turn on. this process repeats at a rate that is dependant upon the load current demand. when the mode pin is driven to a logic high (or left ? oat- ing) the LTC3541 operates in pulse-skip mode for low output voltage ripple. in this mode, the LTC3541 continues to switch at a constant frequency down to very low cur- rents, where it will begin skipping pulses used to control the main (top) switch to maintain the proper average inductor current. if the input supply voltage is decreased to a value ap- proaching the output voltage, the duty cycle of the buck is increased toward maximum on-time and 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the main switch and the inductor. vldo/linear regulator loop in the LTC3541, the vldo and linear regulator loops consist of an ampli? er and n-channel mosfet output stages that, when connected with the proper external components, will servo the output to maintain a regulator output volt- age, lv out . the internal reference voltage provided to the ampli? er is 0.4v allowing for a wide range of output volt- ages. loop con? gurations enabling the vldo or the linear regulator are stable with an output capacitance as low as 2.2f and as high as 100f. both the vldo and the linear regulators are capable of operating with an input voltage, v in , as low as 2.7v, but are subject to the constraint that v in must be greater than lv out + 1.4v. the vldo is designed to provide up to 300ma of output current at a very low lv in to lv out voltage. this allows a clean, secondary, analog supply voltage to be provided with a minimum drop in ef? ciency. the vldo is provided with thermal protection that is designed to disable the vldo function when the output, pass transistors junction temperature reaches approximately 160c. in addition to thermal protection, short-circuit detection is provided to disable the vldo function when a short-circuit condition is sensed. this circuit is designed such that an output current of approximately 1a can be provided before this circuit will trigger. as detailed in the electrical characteristics, the vldo regulator will be out of regulation when this event occurs. both the thermal and short-circuit faults when
LTC3541 10 3541f detected are treated as catastrophic fault conditions. the LTC3541 will be reset upon the detection of either event. the n-channel mosfet incorporated in the vldo has its drain connected to the lv in pin as shown in figure 1. to ensure reliable operation, the lv in voltage must be stable before the vldo is enabled. for the case where the volt- age on the lv in pin is supplied by the buck regulator, the internal power supply sequencing logic assures voltages are applied in the appropriate manner. for the case where an external supply is used to power the lv in pin, the volt- age on the lv in pin must be stable before the envldo pin is brought from a low to a high. further, the external lv in voltage must be reduced in conjunction with v in whenever v in is pulled low or removed. the linear regulator is designed to provide a lower output current (30ma) than that available from the vldo. the linear regulators output pass transistor has its drain tied to the v in rail. this allows the linear regulator to be turned on prior to, and independent of, the buck regulator which ordinarily drives the vldo. the linear regulator is provided with thermal protection that is designed to disable the linear regulator function when the output pass transistors junction temperature reaches approximately 160c. in addition to thermal protection, short-circuit detection is provided to disable the linear regulator function when a short-circuit condition is sensed. this circuit is designed such that an output current of approximately 120ma can be provided before this circuit will trigger. as detailed in the electrical characteristics, the linear regulator will be out of regulation when this event occurs. both the thermal and short-circuit faults are treated as catastrophic fault conditions. the LTC3541 will be reset upon the detection of either event. the n-channel mosfet incorporated in the linear regulator has its drain connected to the v in pin as shown in figure 1. the size of this mosfet and its associated power bussing is designed to accommodate 30ma of dc current. currents above this can be supported for short periods as stipulated in the absolute maximum ratings section. transitioning from linear regulator mode to vldo mode, accomplished by bringing enbuck from a logic low to a logic high while envldo is a logic high, is designed to be as seamless and transient free as possible. the precise transient response of lv out due to this transition is a function of c out and the load current. waveforms given in the typical performance characeristics show typical transient responses using the minimum c out of 2.2f and load currents of 1ma and 30ma respectively. generally, the amplitude of any transients present will decrease as c out is increased. to ensure reliable operation and adherence to the load regulation limits presented in the electrical characteristics table, the load current must not exceed the linear regulator i out limit of 30ma within 20ms after enbuck has transitioned to a logic high. the 300ma i out limit of vldo applies thereafter. further, for con? gurations that do not use the LTC3541s buck regulator to provide the vldo input voltage (lv in ), the user must ensure a stable lv in voltage is present no less than 1ms prior to enbuck transitioning to a logic high. in a similar manner, transitioning from vldo mode to linear regulator mode, accomplished by bringing enbuck from a high low to a logic low while envldo is a logic high, is designed to be as seamless and transient free as possible. again, the precise transient response of lv out due to this transition is a function of c out and the load current. waveforms given in the typical performance characeristics show typical transient responses using the minimum c out of 2.2f and load currents of 1ma and 30ma respectively. generally, the amplitude of any transients present will decrease as c out is increased. to ensure reliable operation and adherence to the load regulation limits presented in the electrical characterstics table, the load current must not exceed the linear regulator i out limit of 30ma 1ms prior to enbuck transitioning to a logic low and thereafer. further, for con? gurations that do not use the LTC3541s buck regulator to provide the vldo input voltage (lv in ), the user must continue to ensure a stable lv in voltage no less than 1ms after enbuck has transitioned to a logic low. operatio u
LTC3541 11 3541f applicatio s i for atio wu u u the basic LTC3541 application circuit is shown on the ? rst page of this data sheet. external component selection is driven by the load requirement and requires the selection of l, followed by c in , c out , and feedback resistor values for the buck and the selection of the output capacitor and feedback values for the vldo and linear regulator. buck regulator inductor selection for most applications, the appropriate inductor value will be in the range of 1.5h to 3.3h with 2.2h the most commonly used. the exact inductor value is chosen largely based on the desired ripple current and burst ripple performance. generally, large value inductors re- duce ripple current, and conversely, small value inductors produce higher ripple current. higher v in or v out may also increase the ripple current as shown in equation 1. a reasonable starting point for setting ripple current is i l = 200ma (40% of 500ma). ?= ()( ) ? ? ? ? ? ? ? i fl v v v l out out in 1 1 (1) the dc current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. thus, a 600ma rated inductor should be enough for most applications (500ma + 100ma). for better ef? ciency, choose a low dc resis- tance inductor. inductor core selection different core materials and shapes will change the size/current and price/current relationship of an induc- tor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. the choice of which style inductor to use often depends more on the price vs size requirement and any radiated ? eld/emi requirements rather than what the LTC3541 requires to operate. table 2 shows some typical surface mount inductors that work well in LTC3541 applications. c in and c out selection in continuous mode, the source current of the top mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: ci vvv in omax out in out required i rms ? ? () ? ? ? ? 1/ 22 v in this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is common- ly used for design. note that the capacitor manufacturers ripple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capaci- tor or choose a capacitor rated at a higher temperature than required. always consult the manufacturer with any question regarding proper capacitor choice. the selection of c out for the buck regulator is driven by the desired buck loop transient response, required effective series resistance (esr) and burst ripple performance. the LTC3541 minimizes the required number of external components by providing internal loop compensation for the buck regulator loop. loop stability, transient re- sponse and burst performance can be tailored by choice of output capacitance. for many applications, desirable stability, trnasient response and ripple performance can table 2. representative surface mount inductors part number value (h) dcr ( max) max dc current (a) size w l h (mm 3 ) sumida cdrh3d23 1.0 1.5 2.2 3.3 0.025 0.029 0.038 0.048 2.0 1.5 1.3 1.1 3.9 3.9 2.4 sumida cmd4d06 2.2 3.3 0.116 0.174 0.950 0.770 3.5 4.3 0.8 coilcraft me3220 1.0 1.5 2.2 3.3 0.058 0.068 0.104 0.138 2.7 2.2 1.0 1.3 2.5 3.2 2.0 murata lqh3c 1.0 2.2 0.060 0.097 1.00 0.79 2.5 3.2 2.0 sumida cdrh2d11/hp 1.5 2.2 0.06 0.10 1.00 0.72 3.2 3.2 1.2
LTC3541 12 3541f applicatio s i for atio wu u u be obtained by choosing an output capacitor value of 10f to 22f. typically, once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. the output ripple v out is determined by: ??? + ? ? ? ? ? ? v i esr fc out l out 1 8 where f = operating frequency, c out = output capacitance and i l = ripple current in the inductor. for a ? xed output voltage, the output ripple is highest at maximum input voltage since i l increases with input voltage. aluminum electrolytic and dry tantalum capacitors are both available in surface mount con? gurations. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalum. these are specially constructed and tested for low esr so they give the lowest esr for a given volume. other capacitor types include sanyo poscap, kemet t510 and t495 series, and sprague 593d and 595d series. consult the manufacturer for other speci? c recommendations. using ceramic input and output capacitors high value, low cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating, and low esr make them ideal for switching regulator applications. since the LTC3541s control loop does not depend on the output capacitors esr for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. however, care must be taken when ceramic capacitors are used at the input and the output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in , large enough to damage the part. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage charac- teristics of all the ceramics for a given value and size. output voltage programming the output voltage is set by tying buckfb to a resistive divider according to the following formula: vv r r out =+ ? ? ? ? ? ? 08 1 2 1 . since the impedance at the buckfb pin is dependant upon the resistor divider network used, and phase shift due to this impedance directly impacts the transient response of the buck, r1 should be chosen <125k. in addition, stray capacitance at this pin should be minimized (<5pf) to pre- vent excessive phase shift. finally, special attention should be given to any stray capacitances that can couple external signals onto the buckfb pin producing undesirable output ripple. for optimum performance connect the buckfb pin to r1 and r2 with a short pcb trace and minimize all other stray capacitance to the buckfb pin. the external resistive divider is connected to the output, allowing remote voltage sensing as shown in figure 6. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ( i load ? esr), where esr is the effective series figure 6. setting the LTC3541 output voltage buckfb gnd LTC3541 0.8v v out 5v r2 r1 3541 f06
LTC3541 13 3541f applicatio s i for atio wu u u resistance of c out . i load also begins to charge or dis- charge c out , which generates a feedback error signal. the regulator loop then acts to return v out to its steady-state value. during this recovery time v out can be monitored for overshoot or ringing that would indicate a stability problem. for a detailed explanation of switching control loop theory see application note 76. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in paral- lel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 ? c load ). thus, a 10f capacitor charging to 3.3v would require a 250s rise time, limiting the charging current to about 130ma. vldo/linear regulator adjustable output voltage the LTC3541 lv out output voltage is set by the ratio of two external resistors as shown in figure 7. the device servos lv out to maintain the lfb pin voltage at 0.4v (referenced to ground). thus, the current in r1 is equal to 0.4v/r1. for good transient response, stability, and accuracy, the current in r1 should be at least 2a, thus the value of r1 should be no greater than 200k. the current in r2 is the current in r1 plus the lfb pin bias current. since the lfb pin bias current is typically <10na, it can be ignored in the output voltage calculation. the output voltage can be calculated using the formula in figure 8. note that in shutdown the output is turned off and the divider current will be zero once c out is discharged. the LTC3541 vldo and linear regulator loops operate at a relatively high gain of C3.5v/ma and C3.4v/ma respectively, referred to the lfb input. thus, a load cur- rent change of 1ma to 300ma produces a 1.05mv drop at the lfb input for the vldo and a load current change of 1ma to 30ma produces a 0.1mv drop at the lfb input for the linear regulator. to calculate the change referred to the output simply multiply by the gain of the feedback network (i.e., 1 + r2/r1). for example, to program the output for 1.2v choose r2/r1 = 2. in this example, an output current change of 1ma to 300ma produces 1.05mv ? (1 + 2) = 3.15mv drop at the output. since the lfb pin is relatively high impedance (depending on the resistor divider used), stray capacitance at this pin should be minimized (<10pf) to prevent phase shift in the error ampli? er loop. additionally, special attention should be given to any stray capacitances that can couple external signals onto the lfb pin producing undesirable output ripple. for optimum performance connect the lfb pin to r1 and r2 with a short pcb trace and minimize all other stray capacitance to the lfb pin. output capacitance and transient response the LTC3541 is designed to be stable with a wide range of ceramic output capacitors. the esr of the output capaci- tor affects stability, most notably with small capacitors. a minimum output capacitor of 2.2f with an esr of 0.05 or less is recommended to ensure stability. the LTC3541 vldo is a micropower device and output tran- sient response will be a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. note that bypass capacitors used to decouple individual components powered by the LTC3541 will increase the effective output capacitor value. high esr tantalum and electrolytic capacitors may be used, but a low esr ceramic capacitor must be in parallel at the output. there is no minimum esr or maximum capacitor size requirement. figure 7. programming the LTC3541 () lv out r1 r2 LTC3541 3541 f07 c out r2 r1 v out = 0.4v 1 + lfb gnd
LTC3541 14 3541f applicatio s i for atio wu u u extra consideration must be given to the use of ceramic capacitors. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. the most common dielectrics used are z5u, y5v, x5r and x7r. the z5u and y5v dielectrics are good for providing high capaci- tances in a small package, but exhibit large voltage and temperature coef? cients as shown in figures 8 and 9. when used with a 2v regulator, a 1f y5v capacitor can lose as much as 75% of its initial capacitance over the operating temperature range. the x5r and x7r dielectrics result in more stable characteristics and are usually more suitable for use as the output capacitor. the x7r type has better stability across temperature, while the x5r is less expensive and is available in higher values. in all cases, the output capacitance should never drop below 1f or instability or degraded performance may occur. efficiency considerations generally, the ef? ciency of a regulator is equal to the out- put power divided by the input power times 100%. it is often useful to analyze individual loss terms to determine which terms are limiting ef? ciency and what if any change would yield the greatest improvement. ef? ciency can be expressed as: ef? ciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual loss terms as a per- centage of input power. although all dissipative elements in the circuit produce losses, three main sources typically account for the majority of the losses in the LTC3541 circuits: v in quiescent current, i 2 r losses and loss across vldo output device. when operating with both the buck and vldo active (enbuck and envldo equal to logic high), v in quiescent current loss and loss across the vldo output device dominate the ef? ciency loss at low load currents, whereas the i 2 r loss and loss across the vldo output device dominate the ef? ciency loss at medium to high load currents. at low load currents with the part operating with the linear regulator (enbuck equal to logic low, envldo equal to logic high), ef? ciency is typically dominated by the loss across the linear regulator output device and v in quiescent current. in a typical ef? ciency plot, the ef? ciency curve at very low load currents can be misleading since the actual power lost is of little consequence. 1. the v in quiescent current loss in the buck is due to two components: the dc bias current as given in the electrical characteristics and the internal main switch and synchro- nous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power switches. each time the gate is switched from high to low to high again, a packet of charge, dq, moves from v in to ground. the resulting dq/dt is the current out of v in that is typically larger than the dc bias current and dc bias voltage (v) change in value (%) 3541 f08 20 0 C20 C40 C60 C80 C100 0 4 8 10 26 x5r y5v both capacitors are 1 f, 10v, 0603 case size figure 8. change in capacitor vs bias voltage temperature ( c) C50 C100 change in value (%) C80 C60 C40 C20 x5r y5v 20 C25 02550 3541 f09 75 0 both capacitors are 1 f, 10v, 0603 case size figure 9. change in capacitor vs temperature
LTC3541 15 3541f applicatio s i for atio wu u u proportional to frequency. both the dc bias and gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw , and external inductor r l . in con- tinuous mode, the average output current ? owing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. 3. losses in the vldo/linear regulator are due to the dc bias currents as given in the electrical characteristics and to the (v in C v out ) voltage drop across the internal output device transistor. other losses when the buck and vldo are in operation (enbuck and envldo equal logic high), including c in and c out esr dissipative losses and inductor core losses, generally account for less than 2% total additional loss. thermal considerations the LTC3541 requires the package backplane metal (gnd pin) to be well soldered to the pc board. this gives the dfn package exceptional thermal properties. the power handling capability of the device will be limited by the maximum rated junction temperature of 125c. the LTC3541 has internal thermal limiting designed to protect the device during momentary overload conditions. for continuous normal conditions, the maximum junction temperature rating of 125c must not be exceeded. it is important to give careful consideration to all sources of thermal resistance from junction to ambient. additional heat sources mounted nearby must also be considered. for surface mount devices, heat sinking is accomplished by using the heat-spreading capabilities of the pc board and its copper traces. copper board stiffeners and plated through holes can also be used to spread the heat gener- ated by power devices. to avoid the LTC3541 exceeding the maximum junction temperature, some thermal analysis is required. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t r = p d ? ja where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t a + t r where t a is the ambient temperature. as an example, consider the LTC3541 in dropout at an input voltage v in of 2.9v, an lv in voltage of 1.8v, an lv out voltage of 1.5v, a load current of 200ma for the buck, a load current of 300ma for the vldo and an ambient tem- perature of 85c. from the typical performance graph of switch resistance, the r ds(on) of the p-channel switch at 85c is approximately 0.25 .therefore, power dissipated by the part is approximately: p d = (i loadbuck ) 2 ? r ds(on) + (i loadvldo ) ? ( lv in C lv out ) = 153mw for the 3mm 3mm dfn package, the ja is 43c/w. thus, the junction temperature of the regulator is: t j = 85c + (0.153)(43) = 92c which is well below the maximum junction temperature of 125c. note that at higher supply voltages, the junction tempera- ture is lower due to reduced switch resistance r ds(on) .
LTC3541 16 3541f applicatio s i for atio wu u u pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3541. check the following in your layout: 1. the power traces, consisting of the gnd trace, the sw trace and the v in trace should be kept short, direct and wide. 2. does the lfb pin connect directly to the feedback re- sistors? the resistive divider r1/r2 must be connected between the (+) plate of c out and ground. 3. does the (+) plate of c in connect to v in as closely as possible? this capacitor provides the ac current to the internal power mosfets. 4. keep the switching node, sw, away from the sensitive lfb node. 5. keep the (C) plates of c in and c out as close as pos- sible. design example as a design example, assume the LTC3541 is used in a single lithium-ion battery powered cellular phone ap- plication. the v in will be operating from a maximum of 4.2v down to about 3v. the load current requirement is a maximum of 0.5a for the buck output but most of the time it will be in standby mode, requiring only 2ma. ef- ? ciency at both low and high load currents is important. the output voltage for the buck is 1.8v. the requirement for the output voltage of the vldo is 1.5v while provid- ing up to 0.3a of current. with this information we can calculate l using equation 2: l fi v v v l out out in = () ? () ? ? ? ? ? ? ? 1 1 (2) substituting v out = 1.8v, v in = 3.6v (typ), i l = 0.2ma and f = 2.25mhz in equation 3 gives: l v mhz ma v v h =? ? ? ? ? ? ? = 18 2 25 200 1 18 36 2 . .( ) . . (3) a 2.2h inductor works well for this application. for best ef? ciency choose a 600ma or greater inductor with less than 0.2 series resistance. c in will require an rms current rating of at least 0.25a = i load(max) /2 at temperature . c out for the buck is chosen as 22f with an esr of less than 0.2 . in most cases, a ceramic capacitor will satisfy this requirement. for the feedback resistors of the buck, choose r1 = 80k. r2 can then be calculated from equation 4 to be: r v rk out 2 08 1 1 100 =? ? ? ? ? ? ? = . (4) for the feedback resistors of the vldo, choose r1 = 200k. r2 can then be calculated from equation 5 to be: r v rk out 2 04 1 1 550 =? ? ? ? ? ? ? = . c out for the vldo is chosen as 2.2f.
LTC3541 17 3541f dual output with minimal external components using auto start-up sequence, buck in burst mode operation for high ef? ciency down to low load currents sw v in enbuck buckfb lv in envldo mode gnd lfb lv out pgnd LTC3541 v out2 1.8v 300ma 3541 ta02a 2.2 h 10 f 2.2 f 22pf v in 3.2v to 4.2v 154k 73k 165k 576k v out1 2.5v 500ma dual output with minimal external components using auto start-up sequence, buck in pulse skip mode for low noise operation sw v in enbuck buckfb lv in envldo mode gnd lfb lv out pgnd LTC3541 v out2 1.8v 300ma 3541 ta03a 2.2 h 10 f 2.2 f 22pf v in 3.2v to 4.2v 154k 73k 165k 576k v out1 2.5v 500ma typical applicatio s u v out 2v/div lv out 2v/div v in 2v/div i vout = 200ma i lvout = 300ma 4ms/div 3541 ta02b v out 2v/div lv out 2v/div v in 2v/div i vout = 200ma i lvout = 300ma 4ms/div 3541 ta03b
LTC3541 18 3541f dual output using minimal external components with v out2 controlled by external logic signal, buck in burst mode operation for high ef? ciency down to low load currents dual output using minimal external components with v out1 controlled by external logic signal, buck in burst mode operation for high ef? ciency down to low load currents typical applicatio s u sw v in enbuck buckfb lv in envldo mode gnd lfb lv out pgnd LTC3541 v out2 1.8v 300ma 3541 ta04a 2.2 h 10 f 2.2 f 22pf v in 3.2v to 4.2v 154k 73k 165k 576k v out1 2.5v 500ma sw v in enbuck buckfb lv in envldo mode gnd lfb lv out pgnd LTC3541 v out2 1.5v 3541 ta05a 2.2 h 10 f 2.2 f 22pf v in 2.9v to 4.2v 143k 115k 150k 412k v out1 1.8v v out 2v/div lv out 2v/div v in 2v/div i vout = 200ma i lvout = 300ma 4ms/div 3541 ta04b v out 2v/div lv out 2v/div v in 2v/div i vout = 200ma i lvout = 30ma 4ms/div 3541 ta05b
LTC3541 19 3541f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd10) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc
LTC3541 20 3541f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 1206 ? printed in usa related parts part number description comments lt ? 3023 dual, 2x100ma, low noise micropower ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.30v, i q = 40a, i sd < 1a, v out = adj, dfn, ms packages, low noise < 20v rms(p-p) , stable with 1f ceramic capacitors lt3024 dual, 100ma/500ma, low noise micropower ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.30v, i q = 60a, i sd < 1a, v out = adj, dfn, tssop packages, low noise < 20v rms(p-p) , stable with 1f ceramic capacitors ltc3025 300ma, micropower vldo linear regulator v in : 0.9v to 5.5v, v out(min) = 0.4v, 2.7v to 5.5v bias voltage required, v do = 45mv, i q = 50a, i sd < 1a, v out = adj, dfn packages, stable with 1f ceramic capacitors ltc3407 dual synchronous 600ma synchronous step-down dc/dc regulator 1.5mhz constant frequency current mode operation, v in from 2.5v to 5.5v, v out down to 0.6v, dfn, ms packages ltc3407-2 dual synchronous 800ma synchronous step-down dc/dc regulator, 2.25mhz 2.25mhz constant frequency current mode operation, v in from 2.5v to 5.5v, v out down to 0.6v, dfn, ms packages ltc3445 i 2 c controllable buck regulator with two ldos and backup battery input 600ma, 1.5mhz current mode buck regulator, i 2 c programmable v out from 0.85v to 1.55v, two 50ma ldos, backup battery input with powerpath control, qfn package ltc3446 triple output step-down converter 1a output buck, two each 300ma vdlos v in : 2.7v to 5.5v, v out(min) buck = 0.8v, v out(min) vldo = 0.4v out(min) , 14-pin dfn package ltc3448 600ma (i out ), high ef? ciency, 1.5mhz/2.25mhz synchronous step-down regulator with ldo mode v in : 2.7v to 5.5v, v out(min) = 0.6v, switches to ldo mode at 3a, dd8, ms8/e packages LTC3541-2 high ef? ciency buck plus vldo regulator v in : 2.9v to 5.5v, v out(buck) = 1.875v, v out(vldo) = 1.5v, 3mm 3mm 10-pin dfn package LTC3541-3 high ef? ciency buck plus vldo regulator v in : 3v to 5.5v, v out(buck) = 1.8v, v out(vldo) = 1.575v, 3mm 3mm 10-pin dfn package ltc3547 dual 300ma (i out ), 2.25mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd < 1a, 8-pin dfn package ltc3548/ltc3548-1 ltc3548-2 dual 800ma/400ma (i out ), 2.25mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd < 1a, dfn and 10-pin ms packages ltc3700 step-down dc/dc controller with ldo regulator v in from 2.65v to 9.8v, constant frequency 550khz operation powerpath is a trademark of linear technology corporation.

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